
module Counter_pHi2 ( Count, Clock, CountEnable, CountReset );
  output [2:0] Count;
  input Clock, CountEnable, CountReset;
  wire   N0, N1, N2, ClockWire, N3, N4, N5, N6;

  \**SEQGEN**  \CountReg_reg[2]  ( .clear(CountReset), .preset(1'b0), 
        .next_state(N6), .clocked_on(ClockWire), .data_in(1'b0), .enable(1'b0), 
        .Q(Count[2]), .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(
        1'b0), .synch_enable(1'b1) );
  \**SEQGEN**  \CountReg_reg[1]  ( .clear(CountReset), .preset(1'b0), 
        .next_state(N5), .clocked_on(ClockWire), .data_in(1'b0), .enable(1'b0), 
        .Q(Count[1]), .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(
        1'b0), .synch_enable(1'b1) );
  \**SEQGEN**  \CountReg_reg[0]  ( .clear(CountReset), .preset(1'b0), 
        .next_state(N4), .clocked_on(ClockWire), .data_in(1'b0), .enable(1'b0), 
        .Q(Count[0]), .synch_clear(1'b0), .synch_preset(1'b0), .synch_toggle(
        1'b0), .synch_enable(1'b1) );
  ADD_UNS_OP add_40 ( .A(Count), .B(1'b1), .Z({N6, N5, N4}) );
  SELECT_OP C24 ( .DATA1(Clock), .DATA2(1'b0), .CONTROL1(N0), .CONTROL2(N1), 
        .Z(ClockWire) );
  GTECH_BUF B_0 ( .A(CountEnable), .Z(N0) );
  GTECH_BUF B_1 ( .A(N2), .Z(N1) );
  GTECH_NOT I_0 ( .A(CountEnable), .Z(N2) );
  GTECH_NOT I_1 ( .A(CountReset), .Z(N3) );
  GTECH_BUF B_2 ( .A(N3) );
endmodule


module Converter_pHi2_pPad5 ( OutBus, InBus, Enable );
  output [7:0] OutBus;
  input [2:0] InBus;
  input Enable;
  wire   N0, N1, N2, N3, N4, N5, N6, N7;

  \**TSGEN**  \OutBusGate_tri[7]  ( .\function (1'b0), .three_state(N0), 
        .\output (OutBus[7]) );
  GTECH_NOT I_0 ( .A(Enable), .Z(N0) );
  \**TSGEN**  \OutBusGate_tri[6]  ( .\function (1'b0), .three_state(N1), 
        .\output (OutBus[6]) );
  GTECH_NOT I_1 ( .A(Enable), .Z(N1) );
  \**TSGEN**  \OutBusGate_tri[5]  ( .\function (1'b0), .three_state(N2), 
        .\output (OutBus[5]) );
  GTECH_NOT I_2 ( .A(Enable), .Z(N2) );
  \**TSGEN**  \OutBusGate_tri[4]  ( .\function (1'b0), .three_state(N3), 
        .\output (OutBus[4]) );
  GTECH_NOT I_3 ( .A(Enable), .Z(N3) );
  \**TSGEN**  \OutBusGate_tri[3]  ( .\function (1'b0), .three_state(N4), 
        .\output (OutBus[3]) );
  GTECH_NOT I_4 ( .A(Enable), .Z(N4) );
  \**TSGEN**  \OutBusGate_tri[2]  ( .\function (InBus[2]), .three_state(N5), 
        .\output (OutBus[2]) );
  GTECH_NOT I_5 ( .A(Enable), .Z(N5) );
  \**TSGEN**  \OutBusGate_tri[1]  ( .\function (InBus[1]), .three_state(N6), 
        .\output (OutBus[1]) );
  GTECH_NOT I_6 ( .A(Enable), .Z(N6) );
  \**TSGEN**  \OutBusGate_tri[0]  ( .\function (InBus[0]), .three_state(N7), 
        .\output (OutBus[0]) );
  GTECH_NOT I_7 ( .A(Enable), .Z(N7) );
endmodule


module ParamCounterTop ( Count, Clock, CountEnable, CountReset, OutEnable );
  output [7:0] Count;
  input Clock, CountEnable, CountReset, OutEnable;

  wire   [2:0] Xfer;

  Counter_pHi2 Counter01 ( .Count(Xfer), .Clock(Clock), .CountEnable(
        CountEnable), .CountReset(CountReset) );
  Converter_pHi2_pPad5 Converter01 ( .OutBus(Count), .InBus(Xfer), .Enable(
        OutEnable) );
endmodule

